Micro-systems technology includes the making of a variety of micro-structures where the functionality depends on the micro-structure being released from a substrate, and maintaining some physical space around the functional element during operation. This often causes complexity in the packaging processes for such micro-structures, because (a) the micro-structure is usually too fragile to withstand the operation of dicing of the substrate (thus needing some protection during this dicing process), (b) the function of the device needs the maintenance of a cavity around the micro-structure during functional operation (not necessarily during the packaging process), and (c) this cavity may or may not need to be sealed from the outside ambient gas during functional operation. These factors lead to considerable increases in complexity over the simplest (least expensive) chip packaging processes, where the dice (chips) can be simply immersed in plastic packaging material.
The last few steps (“back-end”) of such processes must involve, in unspecified order, the creation (release) of the micro-structure, the dicing of the wafer into chips, the affixing of the individual dice to packages and subsequent bonding to the bonding pads, and the closing of the package. The order in which these actions are accomplished is the subject of considerable complexity and investigation among researchers and industrial entities.
In mainstream microelectronics processes, where there are no suspended microstructures, and no cavity needs to be maintained, there are at least two straightforward procedures: (a) finish substrate processing, dice the substrate into individual die (singulate), then bond to the bonding pads and package in injection-molded plastic package; (b) finish substrate processing, deposit and pattern photosensitive material for creation of flip-chip bonding nubs, deposition of bonding nubs, dicing, then bond the chip to its carrier using the bonding nubs.
Methods are being developed for “wafer-level” packaging. These methods involve the affixing of a substrate-sized cover to the wafer at or near the end of the process, whose purposes are to seal a cavity around the micro-structure, as well as to protect the micro-structure during subsequent packaging processes such as dicing. This can work well for subsequent simple plastic packaging. However, a disadvantage is that such a wafer-level cover may be too thick to allow flip-chip bonding, or may be incompatible with flip-chip bonding for other reasons.
Moreover, since it is essential to facilitate the integration of micro-structures and cavities with fabrication processes of mainstream integrated circuits, there is a need to address the problem experienced by the micro-structure during the packaging process.